Atilẹba Tuntun XC18V04VQG44C Aami Iṣura FPGA Field Programmable Gate Array Logic IC Chip Integrated Circuits
Ọja eroja
ORISI | Apejuwe |
Ẹka | Awọn iyika Iṣọkan (ICs) |
Mfr | AMD Xilinx |
jara | - |
Package | Atẹ |
Ipo ọja | Atijo |
Eto Iru | Ni Eto Eto |
Iranti Iwon | 4Mb |
Foliteji – Ipese | 3V ~ 3.6V |
Awọn iwọn otutu ti nṣiṣẹ | 0°C ~ 70°C |
Iṣagbesori Iru | Oke Oke |
Package / Ọran | 44-TQFP |
Package Device Olupese | 44-VQFP (10× 10) |
Nọmba Ọja mimọ | XC18V04 |
Awọn iwe aṣẹ & Media
ORIṢẸRẸ | ỌNA ASOPỌ |
Awọn iwe data | XC18V00 jara |
Alaye Ayika | Xiliinx RoHS Iwe-ẹri |
PCN Obsolescence/ EOL | Awọn ẹrọ pupọ 01/Jun/2015 |
PCN Apá Ipò Change | Awọn ẹya tun ṣiṣẹ 25/Apr/2016 |
HTML Datasheet | XC18V00 jara |
Ayika & okeere Classifications
IFA | Apejuwe |
Ipo RoHS | ROHS3 ni ibamu |
Ipele Ifamọ Ọrinrin (MSL) | 3 (wakati 168) |
Ipò REACH | REACH Ko ni ipa |
ECCN | 3A991B1B1 |
HTSUS | 8542.32.0071 |
Afikun Resources
IFA | Apejuwe |
Standard Package | 160 |
Iranti Xilinx - Awọn iṣeduro Iṣeto fun awọn FPGA
Xilinx ṣafihan XC18V00 jara ti inu-eto iṣeto ni awọn PROMs (olusin 1).Awọn ẹrọ inu ẹbi 3.3V yii pẹlu 4-megabit, 2-megabit, 1-megabit, ati 512-kilobit PROM ti o pese ọna ti o rọrun-touse, ọna ti o ni iye owo fun atunṣe ati titoju awọn bitstreams iṣeto ni Xilinx FPGA.
Nigbati FPGA ba wa ni ipo Serial Titunto, o ṣe agbekalẹ aago iṣeto kan ti o ṣe awakọ PROM.Akoko iwọle kukuru lẹhin CE ati OE ti ṣiṣẹ, data wa lori pin PROM DATA (D0) ti o ni asopọ si pin FPGA DIN.Data tuntun wa ni akoko iwọle kukuru lẹhin eti aago kọọkan ti o ga soke.FPGA n ṣe agbekalẹ nọmba ti o yẹ fun awọn iṣọn aago lati pari iṣeto naa.Nigbati FPGA ba wa ni ipo Serial Slave, PROM ati FPGA jẹ aago nipasẹ aago ita.
Nigbati FPGA ba wa ni Titunto Yan ipo MAP, FPGA n ṣe agbekalẹ aago iṣeto kan ti o wakọ PROM.Nigbati FPGA ba wa ni Parallel Ẹrú tabi Ẹrú Yan MAP mode, oscillator itagbangba n ṣe agbekalẹ aago iṣeto ti o wakọ PROM ati FPGA.Lẹhin ti CE ati OE ti ṣiṣẹ, data wa lori awọn pinni DATA PROM (D0-D7).Data tuntun wa ni akoko iwọle kukuru lẹhin eti aago kọọkan ti o ga soke.Awọn data ti wa ni clocked sinu FPGA lori awọn wọnyi nyara eti CCLK.Oscillator ti nṣiṣẹ ọfẹ le ṣee lo ni Parallel Slave tabi Slave Select MAP mode.
Awọn ẹrọ lọpọlọpọ le jẹ cascaded nipa lilo iṣelọpọ CEO lati wakọ igbewọle CE ti ẹrọ atẹle.Awọn igbewọle aago ati awọn abajade DATA ti gbogbo awọn PROMs ninu pq yii jẹ asopọ.Gbogbo awọn ẹrọ wa ni ibaramu ati pe o le wa ni cascaded pẹlu awọn ọmọ ẹgbẹ miiran ti ẹbi tabi pẹlu XC17V00 eto-akoko kan-akoko PROM idile.